JOHNSON COUNTER AND RING COUNTER
JOHNSON COUNTER
Just as people use watches and calendars to keep track of important events in their lives, digital applications use counters to keep track of important processes. When you go do your laundry, for instance, the computer in your washing machine uses counters to track the different cleaning cycles that the machine goes through.
TRUTH TABLE
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FF Output
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Decoder
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Count
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A
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B
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C
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E
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AND
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0
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0
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0
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0
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A’E’
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G1
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1
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0
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0
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0
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AB’
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G2
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1
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1
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0
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0
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BC’
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G3
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1
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1
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1
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0
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CE’
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G4
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1
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1
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1
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1
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AE
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G5
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0
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1
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1
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1
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A’B
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G6
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0
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0
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1
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1
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B’C
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G7
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0
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0
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0
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1
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C’E
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G8
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Figure 1:
— Four-Stage Switch-Tail Ring Counter
Decoding the Johnson Counter
Ring counters
Decoding the Johnson Counter
Ring counters
Counters come in
all shapes and forms; similarly to how cars come in all shapes and forms.
The Johnson
counter in the main interactive circuit is just one type of counter. It has
four D-flipflops, and it counts from G1 to G8. This mathematical relationship,
where 2* flipflops = count, is a special property of the Johnson counter. To
count from one to ten we would need five flipflops; from one to thirty we would
need fifteen flipflops. In addition to the four D-flipflops, the circuit has
eight two-input AND gates. This too is a peculiarity of the Johnson counter:
the circuit uses one two-input AND gate per count, so that the number of AND
gates in the circuit is twice the number of D-flipflops.
From another
perspective, the Johnson counter is the combination of adecoder and
a ring counter, a switch-tail ring counter to be exact. From that
view, our counter is a four bit switch-tail ring counter connected to a
four-to-eight bit decoder.
Figure 1 below
shows the ring counter that serves as the backbone of the Johnson counter.
Figure 1 is interactive, so you can play with it. The circuit is called a ring
counter because as the clock cycles the circuit moves (or stretches) a signal
through a circular chain of flipflops. The modifier “switch-tail” is to
emphasize that the source of the signal is the negative tail of the circuit; in
other words, the complemented output (E’) of the last flipflop in the chain
feeds the input of the first flipflop in the chain. Hence, the last flipflop
supplies the source signal (E’) that is propagated through the flipflop chain.
An important
detail about the Johnson counter is that the circuit must be initialized
correctly in order for it to generate the desired counting sequence. We
incorporate this idiosyncrasy in the interactive circuits by requiring that you
initialize the circuits by first clicking on an empty area of the board before
counting. If you don’t, the counting sequence you get will be amiss so that you
will have to refresh the browser to do it correctly.
When the Johnson
counter is first initialized, the only asserted piece of wire is the one
connecting the complemented output of the last flipflop (E’) to the input of
the first flipflop in the counter. Then as the clock cycles, the signal
originating from E’ propagates though all the flipflops until it reaches the
output E. Once the propagating signal reaches E, the signal at E’ changes
level, so that at the next clock cycle the new signal emanating from E’ will
start making its way through the counter. Play with the circuit in Figure 1 for
an illustration.
The procedure
that we use to decode the timing signals of the Johnson counter is easy to
follow (see the truth table). To get the first timing signal (state = 0000), we
take the complemented output of the first flipflop (A’) and the complemented
output of the last flipflop (E’) in the chain and combine them into an AND
gate. To get the middle timing signal (state = 1111), we combine the normal
outputs of the first flipflop (A) and the last flipflop (E) into an AND gate.
To get the
signals of the states that fall between 0000 and 1111: starting with the first
flipflop in the counter, we simply combine with an AND gate the normal output
of a flipflop to the complemented output of the flipflop that follows it --
until we reach the last flipflop in the chain. To illustrate, the signals
between 0000 and 1111 are AB’, BC’, and CE’. We stop after reaching E’ because
it is from the last flipflop in the chain.
To get the
signals that come after 1111: starting with the first flipflop, we combine with
an AND gate the complemented output of one flipflop with the normal output of
the flipflop that follows it. And, of course, we do this until the last
flipflop is reached. Again to illustrate, the signals that follow 1111 are A’B,
B’C, and C’E. Here again we stop after E because it is from the last flipflop
in the chain.
As our decoding
procedure just explained how we decoded the timing signals of our four-bit
counter, the procedure can be used to decode a Johnson counter of any arbitrary
length. First, you will need to chain together as many D-flipflops as you need.
Then you just follow our decoding procedure.
RING COUNTER
If the output of
a shift register is fed back to the input. a ring counter results. The data
pattern contained within the shift register will recirculate as long as clock
pulses are applied. For example, the data pattern will repeat every four clock
pulses in the figure below. However, we must load a data pattern. All 0's or all 1's doesn't count. Is a continuous
logic level from such a condition useful?
We make
provisions for loading data into the parallel-in/ serial-out shift register
configured as a ring counter below. Any random pattern may be loaded. The most
generally useful pattern is a single 1.
Loading
binary 1000 into the
ring counter, above, prior to shifting yields a viewable pattern. The data
pattern for a single stage repeats every four clock pulses in our 4-stage
example. The waveforms for all four stages look the same, except for the one
clock time delay from one stage to the next. See figure below.
The circuit
above is a divide by 4 counter.
Comparing the clock input to any one of the outputs, shows a frequency ratio of
4:1. How may stages would we need for a divide by 10 ring counter? Ten stages
would recirculate the 1 every 10 clock pulses.
An alternate
method of initializing the ring counter to 1000 is shown above. The shift waveforms are identical to
those above, repeating every fourth clock pulse. The requirement for
initialization is a disadvantage of the ring counter over a conventional
counter. At a minimum, it must be initialized at power-up since there is no way
to predict what state flip-flops will power up in. In theory, initialization
should never be required again. In actual practice, the flip-flops could
eventually be corrupted by noise, destroying the data pattern. A "self
correcting" counter, like a conventional synchronous binary counter would
be more reliable.
The above binary synchronous counter needs only two stages, but requires
decoder gates. The ring counter had more stages, but was self decoding, saving
the decode gates above. Another disadvantage of the ring counter is that it is
not "self starting". If we need the decoded outputs, the ring counter
looks attractive, in particular, if most of the logic is in a single shift
register package. If not, the conventional binary counter is less complex
without the decoder.
The waveforms
decoded from the synchronous binary counter are identical to the previous ring
counter waveforms. The counter sequence is (QA QB) = (00 01 10 11).