JOHNSON COUNTER AND RING COUNTER

JOHNSON COUNTER AND RING COUNTER

JOHNSON COUNTER

              

Just as people use watches and calendars to keep track of important events in their lives, digital applications use counters to keep track of important processes. When you go do your laundry, for instance, the computer in your washing machine uses counters to track the different cleaning cycles that the machine goes through.

TRUTH TABLE
FF Output					Decoder	Count
A	B	C	E		AND
0	0	0	0		A’E’	G1
1	0	0	0		AB’	G2
1	1	0	0		BC’	G3
1	1	1	0		CE’	G4
1	1	1	1		AE	G5
0	1	1	1		A’B	G6
0	0	1	1		B’C	G7
0	0	0	1		C’E	G8

Figure 1: — Four-Stage Switch-Tail Ring Counter
Decoding the Johnson Counter
Ring counters

Counters come in all shapes and forms; similarly to how cars come in all shapes and forms.

The Johnson counter in the main interactive circuit is just one type of counter. It has four D-flipflops, and it counts from G1 to G8. This mathematical relationship, where 2* flipflops = count, is a special property of the Johnson counter. To count from one to ten we would need five flipflops; from one to thirty we would need fifteen flipflops. In addition to the four D-flipflops, the circuit has eight two-input AND gates. This too is a peculiarity of the Johnson counter: the circuit uses one two-input AND gate per count, so that the number of AND gates in the circuit is twice the number of D-flipflops.

From another perspective, the Johnson counter is the combination of adecoder and a ring counter, a switch-tail ring counter to be exact. From that view, our counter is a four bit switch-tail ring counter connected to a four-to-eight bit decoder.

Figure 1 below shows the ring counter that serves as the backbone of the Johnson counter. Figure 1 is interactive, so you can play with it. The circuit is called a ring counter because as the clock cycles the circuit moves (or stretches) a signal through a circular chain of flipflops. The modifier “switch-tail” is to emphasize that the source of the signal is the negative tail of the circuit; in other words, the complemented output (E’) of the last flipflop in the chain feeds the input of the first flipflop in the chain. Hence, the last flipflop supplies the source signal (E’) that is propagated through the flipflop chain.

An important detail about the Johnson counter is that the circuit must be initialized correctly in order for it to generate the desired counting sequence. We incorporate this idiosyncrasy in the interactive circuits by requiring that you initialize the circuits by first clicking on an empty area of the board before counting. If you don’t, the counting sequence you get will be amiss so that you will have to refresh the browser to do it correctly.

When the Johnson counter is first initialized, the only asserted piece of wire is the one connecting the complemented output of the last flipflop (E’) to the input of the first flipflop in the counter. Then as the clock cycles, the signal originating from E’ propagates though all the flipflops until it reaches the output E. Once the propagating signal reaches E, the signal at E’ changes level, so that at the next clock cycle the new signal emanating from E’ will start making its way through the counter. Play with the circuit in Figure 1 for an illustration.

The procedure that we use to decode the timing signals of the Johnson counter is easy to follow (see the truth table). To get the first timing signal (state = 0000), we take the complemented output of the first flipflop (A’) and the complemented output of the last flipflop (E’) in the chain and combine them into an AND gate. To get the middle timing signal (state = 1111), we combine the normal outputs of the first flipflop (A) and the last flipflop (E) into an AND gate.

To get the signals of the states that fall between 0000 and 1111: starting with the first flipflop in the counter, we simply combine with an AND gate the normal output of a flipflop to the complemented output of the flipflop that follows it -- until we reach the last flipflop in the chain. To illustrate, the signals between 0000 and 1111 are AB’, BC’, and CE’. We stop after reaching E’ because it is from the last flipflop in the chain.

To get the signals that come after 1111: starting with the first flipflop, we combine with an AND gate the complemented output of one flipflop with the normal output of the flipflop that follows it. And, of course, we do this until the last flipflop is reached. Again to illustrate, the signals that follow 1111 are A’B, B’C, and C’E. Here again we stop after E because it is from the last flipflop in the chain.

As our decoding procedure just explained how we decoded the timing signals of our four-bit counter, the procedure can be used to decode a Johnson counter of any arbitrary length. First, you will need to chain together as many D-flipflops as you need. Then you just follow our decoding procedure.

RING COUNTER

If the output of a shift register is fed back to the input. a ring counter results. The data pattern contained within the shift register will recirculate as long as clock pulses are applied. For example, the data pattern will repeat every four clock pulses in the figure below. However, we must load a data pattern. All 0's or all 1's doesn't count. Is a continuous logic level from such a condition useful?

               

We make provisions for loading data into the parallel-in/ serial-out shift register configured as a ring counter below. Any random pattern may be loaded. The most generally useful pattern is a single 1.

                         

Loading binary 1000 into the ring counter, above, prior to shifting yields a viewable pattern. The data pattern for a single stage repeats every four clock pulses in our 4-stage example. The waveforms for all four stages look the same, except for the one clock time delay from one stage to the next. See figure below.

            

The circuit above is a divide by 4 counter. Comparing the clock input to any one of the outputs, shows a frequency ratio of 4:1. How may stages would we need for a divide by 10 ring counter? Ten stages would recirculate the 1 every 10 clock pulses.

               

An alternate method of initializing the ring counter to 1000 is shown above. The shift waveforms are identical to those above, repeating every fourth clock pulse. The requirement for initialization is a disadvantage of the ring counter over a conventional counter. At a minimum, it must be initialized at power-up since there is no way to predict what state flip-flops will power up in. In theory, initialization should never be required again. In actual practice, the flip-flops could eventually be corrupted by noise, destroying the data pattern. A "self correcting" counter, like a conventional synchronous binary counter would be more reliable.

            

The above binary synchronous counter needs only two stages, but requires decoder gates. The ring counter had more stages, but was self decoding, saving the decode gates above. Another disadvantage of the ring counter is that it is not "self starting". If we need the decoded outputs, the ring counter looks attractive, in particular, if most of the logic is in a single shift register package. If not, the conventional binary counter is less complex without the decoder.

             

The waveforms decoded from the synchronous binary counter are identical to the previous ring counter waveforms. The counter sequence is (Q_A Q_B) = (00 01 10 11).

Read More

Frequency Division and Counting

Frequency Division
In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a binary divider, for Frequency Division or as a “divide-by-2″ counter. Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device “feedback” as shown below.

Divide-by-2 Counter

It can be seen from the frequency waveforms above, that by “feeding back” the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( f ÷ 2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave).

This then produces a type of counter called a “ripple counter” and in ripple counters, the clock pulse triggers the first flip-flop whose output triggers the second flip-flop, which in turn triggers the third flip-flop and so on through the chain producing a ripple effect (hence their name) of the timing signal as it passes through the chain.

Of the clock frequency using the appropriate number off FF's, this circuit could devide a frequency by any power of 2.Specifically, using N flip-flops would produce an output frequency from the last FF which is equal to 1/2^N of the input frequency, this application of FF is referred to as frequency division. For frequency division, toggle mode flip-flops are used in a chain as a divide by two counter.

Counting Operation

In addition to functioning as a frequency divider, the circuit of figure 5-45 also operates as a Binary Counter. The clock is actually used for data transfer in these applications. Typically, counters are logic circuits that can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.

Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter where “n” is the number of counter stages used and which is called the Modulus. The modulus or simply “MOD” of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle.

Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2ⁿ-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

On below, the circuit function as a binary counter in which the states of the FFs represent a binary number equivalent to the number of pulses thet have accured.

State Stansition Diagram

Figure 5-47 show how state of the FFs change with each applied clock pulse. Each circle represent one possible state as indicated by the binary number inside the circle.

The arrows connecting one circle to another show how one state changes to another as a clock pulse is applied.

To help describe, analyze, and design counters and other sequential circuit we will use state transition diagram.

MOD Number

The counter of figure 5-45 referred to as a MOD-8 counter, where the MOD number indicates the number of state in the counting sequence. The sequence of states would count in binary from 0000 to 1111 if fourth FF were added.

MOD-16 consist of toal of 16 states. The MOD number of the counter also indicates the frequency division obtained from the last FF.

Refferences : 

2001,Prentice Hall Digital systems principles and applications 8ed, Tocci

http://www.electronics-tutorials.ws/counter/count_1.html

Read More

Development Of Google Glass

This time, I will show you about a Smart Glasses depeloped by Google X. we can called Google Glass, I very interested with this stuff. this Technology is amazing thing from Google Company.
Welcome to a world through Glasses, we can imagine when we wake up in the morning, we just need wear a glasses to see the world. Google Glass has a wide range of applications like, wheater and we can use our voice to search anything we want.

After you see the video what's on your mine? hahaha you want to have it? me to :)
Thanks for reading my blog, please come back soon.

Read More